The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIG. 1, a static random access memory (SRAM) cell 10 is shown to include NMOS transistors 14 and 18 arranged as pass gates. Transistor pairs 22 and 24 each include a PMOS transistor having a first terminal connected to VDD and an NMOS transistor having a second terminal connected to VSS. The transistors 14 and 18 include gates connected to a wordline (WL) 40 and first and second terminals connected between the transistor pairs 22 and 24 and bitlines BL 42 and BLB 44, respectively.
If the wordline is not asserted, the transistors 14 and 18 disconnect the SRAM cell 10 from the bitlines BL 42 and BLB 44.
A read cycle is started by pre-charging the bitlines BL 42 and BLB 44 and then asserting the wordline WL 40, which enables both of the transistors 14 and 18. Then the values stored by the transistor pairs 22 and 24 are transferred to the bitlines by leaving either BL or BLB at its pre-charged value and discharging either BLB or BL. A sense amplifier (not shown) senses whether BL or BLB has a higher voltage to determine whether a 1 or 0 is stored.
During a write cycle, a value to be written is applied to the bitlines BL 42 and BLB 44. When writing a 0, a 0 is applied to the bitlines by setting either BL or BLB to 1 and either BLB or BL to 0. This is similar to applying a reset pulse to an SR-latch, which causes the flip flop to change state. A 1 is written by inverting the values of the bitlines BL 42 and BLB 44. The wordline 40 is then asserted and the value that is to be stored is latched.
SRAM designs use NMOS transistors for the pass gates because the NMOS transistors have higher drive strength (Idsat) than the PMOS transistors for a given size. The higher drive strength provides higher read performance, lower area and reduced power consumption for the SRAM cells as compared to SRAM cells using PMOS pass gates.
FIG. 2 shows an example of a wordline segment 100 that includes SRAM cells 102-1, 102-2, . . . 102-T (collectively SRAM cells 102) that are connected together, where T is an integer greater than one. The wordline segment 100 also includes a buffer 106 including two inverters 108 and 110. Each of the SRAM cells 102 uses NMOS transistors as pass gates as described above.
FIG. 3 shows a memory row 118 including wordline segments 100-1, 100-2, . . . 100-R (collectively wordline segments 100) that are connected together, where R is an integer greater than one. A wordline decoder/driver 120 generates control signals to drive the wordline segments 100. In the example in FIG. 3, R=4 and there are a total of 2×4=8 inverters associated with the memory row 118.